Mid-range FPGA

Mid-range FPGA

Introduction 

 

Gowin’s Mid-range FPGAs provide plentiful on chip resources and features for users:

      Up to 5M bits Embedded Block SRAM supports single and dual port operations, configurable depth and width, flexible read and write modes

       DSP blocks for high performance multiply and accumulation contain up to 80 18X18 Multipliers

       Up to 498 single end IOs support voltage from 1.2V to 3.3V, various drive strength and wide range of IO standards such as LVTTL、LVCOMS、PCI、HSTL、SSTL、RSDS、LVDS etc.

       Easy to use features such as On Chip termination, Hot Socket, Bus Friendly, Open Drain, etc.

       Analog PLL and DLL enable clock multiply, divide, phase & delay adjust, PLL(up to 8) can work from 3MHz to 500MHz

       Up to 8 Channel (preliminary) 3.25Gpbs SERDES

       Support wide range OI protocols such as DDR2、DDR3、ADC、视频、SPI4、PCI Express、Ethernet和CPRI

       Support PBGA256、PBGA484、PBGA672、PBGA1156. May provide more package types per customer request

 

 


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       Family Table

       Device Structure

       CLU Structure

       I/O Structure

       I/O Standard

       ApplicationsDocuments

       IP Source

       Example Solutions

 


Family Table

 

 

Device

gw2a-18

gw2a-55*

Lut

20,736

54,720

FF

15,552

41,040

CLU Array

48X54

76x90

Shadow SRAM

20,736

54,720

Block SRAM Bits

851K

2,424K

Ded Multi 18x18

24

40

Max User IO

336

498(52)

PLLs+DLLs

4+4

6+4

SerDes

-

-

256PBGA

174

-

484PBGA

320

320

672PBGA

384

384

1156PBGA

-

498(52)

 

 

 

 


 

Device Structure

 

 

 

 

I/O Standard

 

 

 

 

 

 


 

Applications Documents

 

      GW2A Application Manual

 

      GW2A Data Sheet